Circuitry for accurately and quickly decoding an input word address to generate a word line enable signal has been under investigation for some time. In particular, such investigation has been directed towards very large scale integration (VLSI) memory circuit design, where both high speed, and low area cost become important factors. As background, a static random access memory (SRAM) is internally organized as a memory cell matrix of rows (or words) and columns. In particular, each SRAM memory cell stores a single bit of information, and associated with that memory cell is a word select or enable line, and a "bit line." In practice, the "bit line" comprises a pair of lines, one having a signal which is the complement of the other. To access the information in the memory cell, a high-voltage is typically applied to a desired word line and the bit line corresponding to the desired column is then accessed. To provide access to the entire memory cell matrix, a memory address externally applied to the device is generally translated into a corresponding row or word address, and a column address. The present invention relates to the means by which the row memory address is translated to provide a word select or enable signal, which is applied to the memory cell matrix for access thereto.
When a high-voltage is applied to a word line, the word line is selected or enabled, and all the SRAM memory cells tied to that word line (i.e., all the memory cells in the selected row) are then available for either read or write operations (i.e., it is said that these cells are enabled and their corresponding bit lines are available for access).
In either a read or write operation, no more than one SRAM cell connected to the same bit line may be simultaneously enabled. When this condition occurs, the so-called "interference" created thereby will create an error, since not more than one memory cell output can exist simultaneously on the same bit line. To avoid producing this kind of interference, two or more word lines must never be active-high simultaneously, or, in other words, there must never be the time overlap between multiple word enable lines.
As the operating speed of prior decoder systems increased, a problem arose: a condition was ultimately reached in which the trailing edge transition of a word line that is turning off overlapped the leading transition of another word line which was turning on. There has been some progress towards solving this problem. In particular, one prior system has addressed this problem by disabling the decoder output (i.e., the word line outputs to the memory cell matrix) while the input memory address is sampled by the decoder (i.e., the cause of the problem there being the delay in generating complement bits of the true address bits. However, the prior art solutions do not adequately address problems arising from delays in the decoder circuitry downstream.
Moreover, even on those prior systems having a word line disable feature, the static logic associated with the decoding portion of the decoder provide non-satisfactory performance with respect to operating speed, and further, incur a large area cost when implemented in a VLSI memory circuit designs.
Accordingly, there is a need to provide an improved SRAM memory word address decoder that minimizes or eliminates one or more of the problems as set forth above.